The ICL 7502 -
Order Code (Instructions)
The ICL 7502 had a very straightforward 16-bit instruction format, as befits a simple, word-orientated machine with a one-dimensional address space. The mill was register-symmetric and all registers (known as X0 to XF) could be used in all instructions, subject to certain limitations on store-indexing as described below. There was no ACCUMULATOR in the traditional sense, or special-purpose registers apart from XF which was the PROGRAMME COUNTER.
A rumour circulated at the time when I was at ICL that the instruction set of the 7502 was designed as a dissertation in computing by by the son of Ed Mack, who was Director of Product Development at that time. Since the 7502 features in no book of computing history that I have ever read I have no clue as to the truth of this rumour. If you know, please tell me.
The topmost 4 bits of the word indicated the instruction type, the tag IMMEDIATE indicates that the low byte of the instruction was an immediate operand:
Store-indexing instructions ran into a problem because there were not enough bits in an instruction to specify a target register, a store address register, an index register and a read/write direction bit. For this instruction the index register could only be one of the same four-register group (X0 to X3, X4 to X7 etc.). A modified version of the store instructions allowed a 2-bit literal offset to be used as a fixed index in place of another register.
Code for the interrupt-handling KERNEL system was developed at Kidsgrove, and written in an assembly language that exploited the CODE feature of the 1900 series CORAL66 compiler. A separate linker would knit together the code modules and create a memory image that could be TELELOADED to a waiting system.
Here is a snatch of code loaded at an arbitary store address (X0100) to write incrementing data characters from 20H to 6FH to video store (VDU 1 located at X4000), and recycling endlessly: